TDA7330B single chip rds demodulator + filter advance data high performance, 57khz bandpass filter (8th order) filter adjustment free and without external components purely digital rds demodulation without external components ari (sk indication) and rds signal quality output 4.332mhz crystal oscillator (8.664mhz optional) low noise mixed bipolar/cmos tech- nology description the TDA7330B is a rds demodulator. it recov- ers the additional inaudible rds information which is transmitted by fm radio broadcasting stations. the output data signal (rdda) and clock signal (rdcl) can be further processed by a suitable rds decoder (microprocessor). the device operates in accordance with the ebu (european broadcasting union) specifications. the ic includes a 2nd order antialiasing input fil- ter, a 57khz switched capacitor band pass filter, a smoothing filter and cross detector, a bit rate clock recovery circuit, a 57khz pll, bi-phase psk decoder, differential decoding circuit, ari in- dication and rds signal quality output. this is advancedinformation on a new product now in developmentor undergoing evaluation. details are subjectto change without notice. notice. april 1993 block diagram dip20 so20 ordering numbers: TDA7330B TDA7330Bd 1/9
absolute maximum ratings symbol parameter value unit v cc supply voltage 7 v t op operating temperature range -40 to 85 c t stg storage temperature -40 to 150 c thermal data symbol description dip20 so20 unit r th j-case thermal resistance junction-case typ. 100 200 c/w pin connection (top view) nr. name description 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 muxin v ref comp fil out gnd t1 t3 t4 osc out osc in t57 rdcl rdda qual ari v cc t2 fsel tm por rds input signal. reference voltage not inverting comparator input (smoothing filter) filter output ground testing output pin (not to be used) testing output pin (not to be used) testing output pin (not to be used) oscillator output oscillator input testing output pin: 57khz clock output rds clock output (1187.5hz) rds data output output for signal quality indication (high = good) output for ari indication (high when rds + ari signals are present) (high when only ari is present) (low when only rds is present) (indefined when no signal is present) supply voltage testing output pin (not to be used) frequency selector pin: open = 4.332mhz, closed to v cc = 8.664mhz test mode pin (open = normal run) (closed to v cc = test mode) reset input for testing (active high) pin function TDA7330B 2/9
electrical characteristics (v cc = 5v, tamb = 25 c; r g = 600 w ; fosc = 4.332mhz; v in = 20mvrms unless otherwise specified) symbol parameter test condition min. typ. max. unit supply v cc supply voltage 4.5 5 5.5 v i s supply current 9 ma r por por pull down resistor pin 20 40 k w por on por threshold 2.5 v filter(measured an pin 4 filout) f c center frequency 56.5 57 57.5 khz bw 3db bandwidth 2.5 3 3.5 khz g gain f = 57khz 18 20 22 db a attenuation d f = +4khz f = 38khz; v i = 500mvrms f = 67khz; v i = 250mvrms 18 50 35 22 80 50 db db db d ph phase non linearity a (see note1) b (see note1) c (see note1) 0.5 1 2 5 7.5 10 deg deg deg r i input impedance 100 160 200 k w s/n signal to noise ratio v i = 3mvrms 30 40 db v i maximum input signal capability f = 19khz; t3 < 40db (see note2) f = 57khz (rds + ari) 1 50 vrms mvrms r l load impedance pin 4 100 k w cross detector ra resistance pin 3-4 15 21 28 k w oscillator f osc oscillator frequency f sel = open (*) f sel = closed to v cc (**) 4.332 8.664 mhz mhz vcll clock input level low (pin 10) 1 v vclh clock input level high (pin 10) 4 v output amplitude (pin 9) 4.5 v pp (*) fsel pin has an internal 40k w pull down resistor a 4.332mhz quartz must be used (**) a 8.664mhz quartz must be used. demodulator d f o max oscillator deviation f sel = open + 1.2 khz s rds rds detection sensitivity 1 mvrms s ari ari detection sensitivity 3 mvrms t lock rds lockup time 100 ms v oh output high voltage i l = 0.5ma; pins 12, 13, 14, 15 4 v v ol output low voltage i l = 0.5ma; pins 12, 13, 14, 15 1 v f rds data rate for rds rdcl pin 1187.5 hz t d rdda transition versus rdcl (see figure 2) 4.3 m sec note(1): the phase non linearity is defined as: d ph = | -2 f f2 + f f1 + f f3 | where f fx is the input-output phase difference at the frequency fx (x = 1,2,3) TDA7330B 3/9
output timing the generated 1187.5hz output clock (rdcl line) is synchronized to the incoming data. according to the internal pll lock condition this data change can results on the falling or on the rising clock edge. whichever clock edge is used by the decoder (ris- ing or falling edge) the data will remain valid for 416.7 m sec after the clock transition. figure 2: rds timing diagram figure 3: test circuit measure f1 (khz) f2 (khz) f3 (khz) d ph max a 56.5 57 57.5 <5 b 56 57 58 <7.5 c 55.5 57 58.5 <10 note(2): the 3th harmonic (57khz) must be less than -40db in respect to the input signal 19khz plus gain. electrical characteristics (continued) TDA7330B 4/9
application suggestion a good dc decoupling between v cc and ground is necessary: a 100nf ceramic ca- pacitor, with low resistance and low inductance at high frequency, directly connected on pin 16 (v cc )and 5 (gnd) is recommended. a small series inductance (100 m h) or resistor (27 w ) may be used for supply line filtering. the layout path pin2 - c2 - pin5 must be as short as possible. if the supply line, after the power on has a soft and disturbed (spikes) slope, a capacitor of 100nf, between por and v cc , is racom- mended. the various testing pins have no sense for the customer. figure 4: p.c. board and component layout of fig. 3 (1:1 scale) TDA7330B 5/9
figure 5: gain vs. frequency figure 6: group delay vs. frequency TDA7330B 6/9
dip20 package mechanical data dim. mm inch min. typ. max. min. typ. max. a1 0.254 0.010 b 1.39 1.65 0.055 0.065 b 0.45 0.018 b1 0.25 0.010 d 25.4 1.000 e 8.5 0.335 e 2.54 0.100 e3 22.86 0.900 f 7.1 0.280 i 3.93 0.155 l 3.3 0.130 z 1.34 0.053 TDA7330B 7/9
so20 package mechanical data dim. mm inch min. typ. max. min. typ. max. a 2.65 0.104 a1 0.1 0.3 0.004 0.012 a2 2.45 0.096 b 0.35 0.49 0.014 0.019 b1 0.23 0.32 0.009 0.013 c 0.5 0.020 c1 45 (typ.) d 12.6 13.0 0.496 0.512 e 10 10.65 0.394 0.419 e 1.27 0.050 e3 11.43 0.450 f 7.4 7.6 0.291 0.299 l 0.5 1.27 0.020 0.050 m 0.75 0.030 s 8 (max.) TDA7330B 8/9
information furnished is believed to be accurate and reliable. however, sgs-thomson microelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of sgs-thomson microelectronics. specifications men- tioned in this publication are subject to change without notice. this publication supersedes and replaces all information previously supplied. sgs-thomson microelectronics products are not authorized for use as critical components in life support devices or systems without ex- press written approval of sgs-thomson microelectronics. ? 1994 sgs-thomson microelectronics - all rights reserved sgs-thomson microelectronics group of companies australia - brazil - france - germany - hong kong - italy - japan - korea - malaysia - malta - morocco - the netherlands - singapore - spain - sweden - switzerland - taiwan - thaliand - united kingdom - u.s.a. TDA7330B 9/9
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